Problems to Think
How are you going to test
VLSI Testing
A 32 bit adder
A 32 bit counter
A 32Mb cache memory
A 107-transistor CPU
A 109-transistor SOC
Introduction.1
NCKUEE-KJLEE
OUTLINE
Introduction
Fault modeling
Fault simulation
Test generation
Automatic test pattern generation
(ATPG)
Design for testability
Built-in self test
Synthesis for testability
An example
VLSI Testing
Introduction.2
NCKUEE-KJLEE
Basic Concept of Testing
Testing: To tell whether a circuit is good or bad
VDD
0
0
0/1
Related fields
Verification: To verify the correctness of a
design
Diagnosis: To tell the faulty site
Reliability: To tell whether a good system will work
correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault
VLSI Testing
Introduction.3
NCKUEE-KJLEE
Why Studying Testing?
Economics!
Reduce test cost (enhance profit)
Automatic test equipment (ATE) is
extremely expensive
Shorten time-to-market
Market dominating or sharing
Guarantee IC quality and reliability
Rule of Ten:
Cost to detect faulty
IC increases by an
order of magnitude
VLSI Testing
Defects detected in
Wafer
Packaged chip
Board
System
Field
Introduction.4
Cost
0.01 0.1
0.1 1
1 10
10 100
100 1000
NCKUEE-KJLEE
Principle of Testing
Input Patterns
-1011
11-00
-0-101--0
0-101
Stored
Correct
Response
Output Response
Circuit
under
Test
(CUT)
1-001
0011-1101
100101-11
Comparator
Test Result
Testing typically consists of
Applying set of test stimuli (input patterns, test
vectors) to inputs of circuit under test (CUT), and
Analyzing output responses
The quality of the tested circuits will depend upon
the thoroughness of the test vectors
VLSI Testing
Introduction.5
NCKUEE-KJLEE
Importance of testing
N = # transistors in a chip
p = prob. (a transistor is faulty)
Pf = prob. (the chip is faulty)
Pf = 1- (1- p) N
If p = 10-6
N = 106
Pf = 63.2%
VLSI Testing
Introduction.6
NCKUEE-KJLEE
Introduction
Integrated Circuits (ICs)
have grown in size and
complexity since the late
1950s
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
Very Large Scale Integration
(VLSI)
Moores Law: scale of ICs
doubles every 18 months
Growing size and complexity
poses many and new testing
challenges
VLSI Testing
Introduction.7
VLSI
M LSI
S
S S
I I
NCKUEE-KJLEE
Importance of Testing
Moores Law results from decreasing feature
size (dimensions)
from 10s of m to 10s of nm for transistors and
interconnecting wires
Operating frequencies have increased from
100KHz to several GHz
Decreasing feature size increases
probability of defects during manufacturing
process
A single faulty transistor or wire results in faulty
IC
Testing required to guarantee fault-free products
VLSI Testing
Introduction.8
NCKUEE-KJLEE
Difficulties in Testing
Fault may occur anytime
-
Design
Process
Package
Field
Fault may occur at any place
Vdd
Vss
VLSI circuit are large
- Most problems encountered in testing are NP-complete
I/O access is limited
VLSI Testing
Introduction.9
NCKUEE-KJLEE
How to do testing
From designers point of view:
Circuit modeling
Fault modeling
Modeling
Logic simulation
Fault simulation
Test generation
ATPG
Design for test
Built-in self test
Testable design
Synthesis for testability
VLSI Testing
Introduction.10
NCKUEE-KJLEE
Circuit Modeling
Functional model--- logic function
- f(x1,x2,...)=...
- Truth table
Behavioral model--- functional + timing
- f(x1,x2,...)=... , Delay = 10
Structural model--- collection of
interconnected components or elements
A
B
E
1
0
C
D
VLSI Testing
1
0
0
F
Introduction.11
NCKUEE-KJLEE
Levels of Structural Description
Switch level
Circuit level
VDD
C
4B
VDD
VDD
C
1
C3
C2
E
Gate level
A
B
Higher/ System level
E
G
C
D
VLSI Testing
Introduction.12
NCKUEE-KJLEE
Fault Modeling
The effects of physical defects
Most commonly used fault model: Single stuck-at
fault
A
B
E
G
C
D
A s-a-1 B s-a-1
A s-a-0 B s-a-0
C s-a-1 D s-a-1
C s-a-0 D s-a-0
E s-a-1 F s-a-1
E s-a-0 F s-a-0
G s-a-1
G s-a-0
14 faults
Other fault models:
- Break faults, Bridging faults, Transistor stuck-open faults,
Transistor stuck-on faults, Delay faults
VLSI Testing
Introduction.13
NCKUEE-KJLEE
Fault Coverage (FC)
# faults detected
FC =
# faults in fault list
Example:
a
b
1
0
1
0
Test
{(0,0)}
{(0,1)}
{(1,1)}
{(0,0),(1,1)}
{(1,0),(0,1),(1,1)}
VLSI Testing
6 stuck-at faults
( a0,a1,b0,b1,c0,c1 )
c1
faults detected
c1
a1,c1
a0,b0,c0
a0,b0,c0,c1
all
Introduction.14
FC
16.67%
33.33%
50.00%
66.67%
100.00%
NCKUEE-KJLEE
Wafer Yield (Chip Yield, Yield)
Good Chip
Faulty Chip
Defects
Wafer
Wafer yield = 12/22 = 0.55
VLSI Testing
Wafer yield = 17/22 = 0.77
Introduction.15
NCKUEE-KJLEE
Testing and Quality
IC
Fabrication
Shipped Parts
Testing
Yield:
Fraction of
good parts
Rejects
Quality:
Defective parts
per million (DPM)
Quality of shipped parts is a function of yield Y and
the test (fault) coverage T
Defect level (DL, reject rate in textbook): fraction of
shipped parts that are defective
VLSI Testing
Introduction.16
NCKUEE-KJLEE
Defect Level, Yield & Fault Coverage
DL = 1 - Y (1-T)
Yield (Y)
50%
75%
90%
95%
99%
90%
90%
90%
90%
VLSI Testing
DL: defect level
Y: yield
T: fault coverage
Fault Coverage (T)
90%
90%
90%
90%
90%
90%
95%
99%
99.9%
Introduction.17
DPM (DL)
67,000
28,000
10,000
5,000
1,000
10,000
5,000
1,000
100
NCKUEE-KJLEE
Logic simulation
To determine how a good circuit should work
Given input vectors, determine the normal
circuit response
A
B
C
C
G
F
E
CC1
I
CC2
RB
CDE C
JE
IR
IF
H
D
VLSI Testing
Introduction.18
NCKUEE-KJLEE
Fault simulation
To determine the behavior of faulty circuits
E s.a.0
A 1
0
B
0
C
0
D
1/0
1
F
1/0
1
Given a test vector, determine all faults that
are
detected by this test vector.
Example:
VLSI Testing
Test vector (1 1) detects
{ a0, b0, c1}
Introduction.19
NCKUEE-KJLEE
Test generation
Given a fault, identify a test to detect this fault
1
Example:
0 1/0
A
B
1/0
F
1
C
To detect D s-a-0, D must be set to 1.
Thus A=B=1.
To propagate fault effect to the primary output
E must be 1. Thus C must be 0.
Test vector: A=1, B=1, C=0
VLSI Testing
Introduction.20
NCKUEE-KJLEE
Automatic Test Pattern Generation
ATPG: Given a circuit, identify a set of test vectors
to detect all faults under consideration.
Input circuit
Form fault list
More faults?
No
Exit
Yes
Fault
dropping
Select a fault
Test generation
Fault simulation
VLSI Testing
Introduction.21
NCKUEE-KJLEE
Difficulties in Test Generation
1. Reconvergent fanout
B 1
VLSI Testing
0/1
s-a-1
Cannot detect the fault
D
1
0/1
Fault detected
0E
Introduction.22
NCKUEE-KJLEE
Difficulties in Test Generation (cont.)
2. Sequential test generation
PIs
Combinational part
Y
Y
VLSI Testing
J
K
CK
Introduction.23
POs
clk
NCKUEE-KJLEE
Testable Design
Design for testability (DFT)
ad hoc techniques
Scan design
Boundary Scan
Built-In Self Test (BIST)
Random number generator (RNG)
Signature Analyzer (SA)
Synthesis for Testability
VLSI Testing
Introduction.24
NCKUEE-KJLEE
Example of ad hoc Techniques
Insert test points
MUX
T/N
VLSI Testing
Introduction.25
NCKUEE-KJLEE
Scan Design
Original design
Modified design
POs PIs
PIs
POs
Combinational
logic
Combinational
logic
SO
FF
SFF
FF
SFF
FF
VLSI Testing
SFF
T/N
Introduction.26
SI
NCKUEE-KJLEE
Scan Cell Design
DI
SI
CK
N/T
(SE)
DI
MUX
DI
Q,SO
CK
Q,SO
DI
SI
+ T
Most cell libraries now have scan cells!
VLSI Testing
Introduction.27
NCKUEE-KJLEE
Scan Register
Combinational
Circuits
SO
Q D
Q D
Q D
SI
SI
SI
Q D
SI
SE
CLK
VLSI Testing
Introduction.28
NCKUEE-KJLEE
Boundary Scan
I/O Pad
Boundary scan cell
Boundary scan path
TRST*
TDI
Sout
Misc. registers
TMS
TCK
TDO
APPLICATION LOGIC
T
A
P
M
U
X
Instruction register
BIST register
Bypass register
Scan register
Sin
TRST*:Test rest (Optional)
TDI: Test data input
TD0: Test data output
TCK: Test clock
TMS: Test mode select
VLSI Testing
Introduction.29
NCKUEE-KJLEE
Boundary Scan (Cont.)
TRST*
TRST*
TDI
APPLICATION LOGIC
Sout
TDI
Sout
Misc. registers
TMS
TCK
BIST register
Bypass register
TCK
Scan register
M
U
X
TDO
TMS
Instruction register
T
A
P
Sin
TDO
T
A
P
TDI
Sout
APPLICATION LOGIC
Scan register
Sin
TDI
Sout
T
A
P
M
U
X
APPLICATION LOGIC
Misc. registers
TMS
TMS
VLSI Testing
BIST register
Bypass register
M
U
X
Misc. registers
TDO
Instruction register
TRST*
TRST*
TCK
APPLICATION LOGIC
Misc. registers
Instruction register
BIST register
Bypass register
TCK
Scan register
Sin
TDO
Introduction.30
T
A
P
M
U
X
Instruction register
BIST register
Bypass register
Scan register
Sin
NCKUEE-KJLEE
Built-In-Self Test (BIST)
Places the job of device testing inside the device
itself
Generates its own stimulus and analyzes its own
response
mux
circuit
under test
BIST
Controller
biston
VLSI Testing
Introduction.31
to system
Response
Analyzer
pattern
generator
from system
good/fail
bistdone
NCKUEE-KJLEE
Built-In-Self Test (BIST) (Cont.)
Two major tasks
- Test pattern generation
- Test result compaction
Usually implemented by linear feedback
shift register
F/F
VLSI Testing
F/F
Introduction.32
F/F
NCKUEE-KJLEE
Random Number Generator (RNG)
F/F
F/F
F/F
F/F
0001
1000
0100
0010
1001
1100
0110
1011
010
1
101
0
1101
1110
1111
0111
0011
0001
(repeat)
1. Generate pseudo random patterns
2. Period is 2n - 1
VLSI Testing
Introduction.33
NCKUEE-KJLEE
Signature Analyzer (SA)
Input sequence 10101111 (8 bits)
G x 1 x 2 x 4 x5 x6 x 7
Time
0
1
.
.
5
6
7
8
P x 1 x 2 x 4 x 5
Input stream Register contents
10101111
00000
1010111
10000
.
.
.
.
101
01111
10
00010
1
00001
00101
Remainder
R x x 2 x 4
VLSI Testing
Introduction.34
Output stream
Initial state
1
01
101
Quotient
1 x2
NCKUEE-KJLEE
Signature Analyzer (SA) (cont.)
A LFSR performs polynomial division
P x : x 5 x 4 x 2 1
Q x : x 2 1
x7 x6 x 4 x 2 x5 x 4 x 2 1
x x x 1
7
P x Q x R x x 7 x 6 x 5 x 4 x 2 1 G x
Probability of aliasing error = 1/2n (n: # of FFs)
VLSI Testing
Introduction.35
NCKUEE-KJLEE
Memory BIST Architecture
Before
After
di
addr
Memory
Module
data
sys_di
data
sys_addr
sys_wen
clk
q
hold_l Memory
rst_l
Module
test_h
si
se
wen
VLSI Testing
Introduction.36
so
NCKUEE-KJLEE
rst_l
clk
hold_l
test_h
di
addr
wen
Memory
Module
compress_h clk
rst
si
se
data
Compressor
sys_addr
sys_d
isys_wen
Algorithm-Based
Pattern Generator
Memory BIST Architecture (Cont.)
q
so
BIST Circuitry
VLSI Testing
Introduction.37
NCKUEE-KJLEE
CPU Test Control Architecture
Scan_i
Scan_o
Scan path
Scan_en
logic
rst_l
clk
Bist
hold_l
test_h
Memory
control
bist_si
bist
decoder
compressor bist_so
scan
decoder
MUX
bist_se
TDO
int_scan mbist
decoder
TDI
IR
TCK
TMS
VLSI Testing
TAP Controller
Introduction.38
NCKUEE-KJLEE
Problems re-thinking
A 32-bit adder --- ATPG
A 32-bit counter --- Design for testability + ATPG
A 32MB Cache memory --- BIST
A 107-transistor CPU --- All test techniques
An SOC
VLSI Testing
Introduction.39
NCKUEE-KJLEE
Conclusions
Testing is becoming a major factor in design optimization
Conventionally, the designer often optimize one of the three
attributes: speed, area, and power.
At present, a fourth attribute is considered: Testability.
Two major fields in testing
ATPG
--- Fault simulation
--- Test generation
Testable design
--- Design for testability
--- Built-in self-test
--- Synthesis for testability
VLSI Testing
Introduction.40
NCKUEE-KJLEE
