Lecture
Lecture 1
1
Introduction
Introduction
VLSI realization process
Verification and test
Ideal and real tests
Costs of testing
Roles of testing
A modern VLSI device - system-on-a-chip
Course outline
Part I: Introduction to testing
Part II: Test methods
Part III: Design for testability
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VLSI
VLSI Realization
Realization Process
Process
Customer’s need
Determine requirements
Write specifications
Design synthesis and Verification
Test development
Fabricatio
n
Manufacturing test
Chips to customer
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Definitions
Definitions
Design synthesis: Given an I/O function, develop a
procedure to manufacture a device using known
materials and processes.
Verification: Predictive analysis to ensure that the
synthesized design, when manufactured, will
perform the given I/O function.
Test: A manufacturing step that ensures that the
physical device, manufactured from the synthesized
design, has no manufacturing defect.
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Verification
Verification vs.
vs. Test
Test
Verifies correctness of Verifies correctness of
design. manufactured hardware.
Performed by simulation, Two-part process:
hardware emulation, or 1. Test generation: software
formal methods. process executed once during
Performed once prior to design
manufacturing. 2. Test application: electrical
Responsible for quality of tests applied to hardware
design. Test application performed on
every manufactured device.
Responsible for quality of
devices.
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Problems
Problems of
of Ideal
Ideal Tests
Tests
Ideal tests detect all defects produced in the
manufacturing process.
Ideal tests pass all functionally good devices.
Very large numbers and varieties of possible
defects need to be tested.
Difficult to generate tests for some real
defects. Defect-oriented testing is an open
problem.
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Real
Real Tests
Tests
Based on analyzable fault models, which may
not map on real defects.
Incomplete coverage of modeled faults due to
high complexity.
Some good chips are rejected. The fraction (or
percentage) of such chips is called the yield
loss.
Some bad chips pass tests. The fraction (or
percentage) of bad chips among all passing
chips is called the defect level.
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Testing
Testing as
as Filter
Filter Process
Process
Good chips Prob(pass test) = high Mostly
w good
Prob(good) = y P ro lo chips
b( =
fa t )
i l es
Fabricated tt
s es
chips a s t)
(p =
ob lo
r w
P
Defective chips Mostly
bad
Prob(bad) = 1- y Prob(fail test) = high
chips
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Costs
Costs of
of Testing
Testing
Design for testability (DFT)
Chip area overhead and yield reduction
Performance overhead
Software processes of test
Test generation and fault simulation
Test programming and debugging
Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost
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Design
Design for for Testability
Testability
(DFT)
(DFT)
DFT refers to hardware design styles or added
hardware that reduces test generation complexity.
Motivation: Test generation complexity increases
exponentially with the size of the circuit.
Example: Test hardware applies tests to blocks A
and B and to internal bus; avoids test generation
for combined A and B blocks.
Int.
Logic bus Logic
PI PO
block A block B
Test Test
input output
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Present
Present and
and Future*
Future*
1997 -2001 2003 - 2006
Feature size (micron) 0.25 - 0.15 0.13 - 0.10
Transistors/sq. cm 4 - 10M 18 - 39M
Pin count 100 - 900 160 - 1475
Clock rate (MHz) 200 - 730 530 - 1100
Power (Watts) 1.2 - 61 2 - 96
* SIA Roadmap, IEEE Spectrum, July 1999
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Cost
Cost of
of Manufacturing
Manufacturing
Testing
Testing in
in 2000AD
2000AD
0.5-1.0GHz, analog instruments,1,024 digital
pins: ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M
Running cost (five-year linear depreciation)
= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/year
Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second
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Roles
Roles of
of Testing
Testing
Detection: Determination whether or not the
device under test (DUT) has some fault.
Diagnosis: Identification of a specific fault that is
present on DUT.
Device characterization: Determination and
correction of errors in design and/or test
procedure.
Failure mode analysis (FMA): Determination of
manufacturing process errors that may have
caused defects on the DUT.
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A
A Modern
Modern VLSI
VLSI Device
Device
System-on-a-chip
System-on-a-chip (SOC)
(SOC)
DSP RAM
core ROM
Data Transmission
terminal medium
Inter- Mixed-
face signal
logic Codec
Figure 18.5 (page 605)
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Course
Course Outline
Outline
Part
Part I:
I: Introduction
Introduction
Basic concepts and definitions (Chapter 1)
Test process and ATE (Chapter 2)
Test economics and product quality (Chapter 3)
Fault modeling (Chapter 4)
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Course
Course Outline
Outline (Cont.)
(Cont.)
Part
Part II:
II: Test
Test Methods
Methods
Logic and fault simulation (Chapter 5)
Testability measures (Chapter 6)
Combinational circuit ATPG (Chapter 7)
Sequential circuit ATPG (Chapter 8)
Memory test (Chapter 9)
Analog test (Chapters 10 and 11)
Delay test and IDDQ test (Chapters 12 and 13)
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Course
Course Outline
Outline (Cont.)
(Cont.)
Part
Part III:
III: DFT
DFT
Scan design (Chapter 14)
BIST (Chapter 15)
Boundary scan and analog test bus (Chapters
16 and 17)
System test and core-based design (Chapter
18)
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