Prerequisite Course

Digital Electronics:
You already have gained the knowledge of the followings:
• Logic gates
• Multiplexer and demultiplexer
• Encoder and decoder
• Programmable Logic devices (PLD)
• Counter
• Registers, memory, flip-flops
• Synchronous, asynchronous operation

1
Microprocessor:
Microprocessor is a multipurpose, programmable,
clock driven, register based electronic device, that Register Array

read binary instruction from a storage device called ALU

memory, accepts binary data as input and processes Control Unit

data according to those instructions and provides

results as outputs. Fig. Microprocessor

2
Application of Microprocessor/Microcontroller:
• Industrial Process control
• Large data processing
• In every decision making smart system

PLC – Programmable Logic Controller

A microprocessor based system that is used in industrial manufacturing process control
with high degree of reliability and ease of programming.

3
List of some earlier microprocessor:

Intel MPU Year Data line/Bus Clock frequency range

Intel 4004 1971 4 bit 740 KHz
Intel 8085 1976 8 bit 6 MHz (max)
Intel 8086 1988 16 bit 10MHZ (max)

Word Length − It depends upon the width of internal data bus, registers, ALU, etc. An 8-bit microprocessor can
process 8-bit data at a time. The word length ranges from 4 bits to 64 bits depending upon the type of the
microcomputer.

What could be the possible reasons for the increased clock speed in MPU?

• Invention of high speed switching devices like CMOS

• high speed and low power logic families like CMOS logic, ECL logic, Bi-CMOS

4
 Block diagram of a typical programmable machine:

Components:
Memory
1. Microprocessor(MPU)
2. Memory
3. Input device Input
4. Output device
MPU Device

Output
Together input and output device are
Device
known as I/O device.

5
 Classification of Microprocessor based system
Based on application
1. Reprogrammable system
Users have the ease to program it.
- personal computer

2. Embedded System
Programs built by manufacturer. Users can only use it.
- Photocopier, Camera, Washing machine, Calculator
In general, Microprocessors are categorized as:
1. General Purpose Microprocessor
System components are discretely connected
Not designed to perform a specific task
- Personal computer

2. Microcontroller
System components are connected in a single board
Designed for specific task
- Any embedded system ( camera, calculator etc.,) 6
 Microcontroller
System Components:

1. Microprocessor(MPU) Memory

2. Memory
3. Input device
Input
4. Output device MPU Device

System components are connected in a single board or in

a single chip Output
Device
So in a Microcontroller a MPU, memory, I/O ports reside
in a single board and not discretely connected.

Fig. Microcontroller
So microcontroller based systems are compact and
tiny.
7
 Bus in Microcomputer System
Bus:
A group of wire comprises a communication system that transfer data/signaling information to the
components inside a computer or between computers.

Address Bus
Different types of Buses:
• Address Bus (Unidirectional) Address
lines
• Data Bus (Bidirectional)
Data Bus
• Control Bus (unidirectional)
Data
lines
Control Bus: MPU Control
Bus
• Memory read control (MORC) Control
• Memory write control (MOWC) lines
• I/O read control (IORC)
• I/O write control (IOWC) Input Device Output
Memory Device

8
9
Example of Microcontroller:
ATmega8, ATmega328P

Arduino UNO:
Open-source microcontroller board based on the Microchip
ATmega328P
10
 Bus in Microcomputer System
Address Bus:
• On this lines the CPU sends out addresses of the memory or I/O devices to write or read from. The number of
location a CPU can address depends on the number of address lines/buses.
• If a CPU has N lines/buses, then total number of location to be addressed is
• Each location can store a byte data (8 bit data).
• A CPU having N lines can address maximum bytes memory.

Data Bus:
• Bidirectional lines
• CPU can read data in from memory or I/O or send data out to memory or I/O

Control Bus:
• Unidirectional lines
• Enable the output of addressed memory or I/O devices.
• Typically 4 control signals transfer through control bus
I. Memory read control (MORC)
II. Memory write control (MOWC)
III. I/O read control (IORC)
IV. I/O write control (IOWC) 11
Memory

12
Memory

13
 8086
Microprocessor Addressing Modes : Memory Access

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

14
 Memory Access
20 Address lines  8086 can address up to 220 = 1M bytes of
memory

However, the largest register is only 16 bits

Physical Address will have to be calculated Physical Address :

Actual address of a byte in memory. i.e. the value which goes out
onto the address bus.

Memory Address represented in the form – Seg : Offset (Eg

- 89AB:F012)

Each time the processor wants to access memory, it takes the

contents of a segment register, shifts it one hexadecimal place to
the left (same as multiplying by 1610), then add the required
offset to form the 20- bit address 16 bytes of contiguous
memory

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
15
16
17
 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 18
multiplexed Intel 8085 (8 bit processor)
 Microprocessor Functional blocks
Various conditions of the results are
Computational Unit; performs
stored as status bits called flags in Internal storage of data
arithmetic and logic operations
flag register

Register array or Data Bus

internal memory
ALU

Generates the address

Instruction decoding
of the instructions to be
Flag Register unit
fetched from the
memory and send
through address bus to
the memory
Timing and
control unit PC/ IP

Control Bus Address Bus

Generates control signals for internal and Decodes instructions; sends information to
external operations of the microprocessor the timing and control unit
19
 8086
Microprocessor Overview

First 16- bit processor released by

INTEL in the year 1978

Originally HMOS, now manufactured

using HMOS III technique

Approximately 29, 000 transistors, 40

pin DIP, 5V supply

Does not have internal clock; external

asymmetric clock source with 33% duty
cycle

20-bit address to access memory  can

address up to 220 = 1 megabytes of
memory space.

20
Architecture

21
 8086
Microprocessor Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
22
 8086
Microprocessor Architecture Bus Interface Unit (BIU)

Dedicated Adder to generate 20 bit

address

Four 16-bit segment registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 23

 8086
Microprocessor Architecture Bus Interface Unit (BIU)

Segment
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access to code
memory is divided address four segments and data in the segments by
into segments of up (256 K bytes within the 1 changing the segment register
to 64K bytes each. M byte of memory) at a content to point to the desired
particular time. segments.

24
 8086
Microprocessor Architecture Bus Interface Unit (BIU)

Segment Code Segment Register

Registers
16-bit

CS contains the base or start of the current code

segment; IP contains the distance or offset from this
address to the next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then
offset is added provided by the IP.

25
 8086
Microprocessor Architecture Bus Interface Unit (BIU)

Segment Data Segment Register

Registers
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or Destination

Index (DI) or a 16-bit displacement are used as offset for
computing the 20-bit physical address.

26
 8086
Microprocessor Architecture Bus Interface Unit (BIU)

Segment Stack Segment Register

Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the Base
Pointer (BP).

27
 8086
Microprocessor Architecture Bus Interface Unit (BIU)

Segment Extra Segment Register

Registers
16-bit

Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-

bit physical address for the destination.

28
 8086
Microprocessor Architecture Bus Interface Unit (BIU)

Segment Instruction Pointer

Registers
16-bit

Always points to the next instruction to be executed

within the currently executing code segment.

So, this register contains the 16-bit offset address

pointing to the next instruction code within the 64Kb of
the code segment area.

Its content is automatically incremented as the execution

of the next instruction takes place.

29
 8086
Microprocessor Architecture Bus Interface Unit (BIU)

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.

This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.

This mechanism is known

as pipelining.

30
 8086
Microprocessor Architecture Execution Unit (EU)

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for performing

arithmetic and logic operation

Four general purpose registers(AX,

BX, CX, DX);

Pointer registers (Stack Pointer,

Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source Index, used as two 8 bit registers as :
Destination Index) each of 16-bits
AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 31
DX can be used as DH and DL
 8086
Microprocessor Architecture Execution Unit (EU)

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

32
 8086
Microprocessor Architecture Execution Unit (EU)

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

33
 8086
Microprocessor Architecture Execution Unit (EU)

EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte

of the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

34
 8086
Microprocessor Architecture Execution Unit (EU)

EU
Registers

35
 8086
Microprocessor Architecture Execution Unit (EU)

EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment
in the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

36
 8086
Microprocessor Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.

37
 8086
Microprocessor Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.

38
 8086
Microprocessor Architecture Execution Unit (EU)

Auxiliary Carry Flag

Carry Flag
Flag Register This is set, if there is a carry from the lowest
nibble, i.e, bit three during addition, or borrow This flag is set, when there is a carry
for the lowest nibble, i.e, bit three, during out of MSB in case of addition or a
subtraction. borrow in case of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the result of This flag is set, if the result of the This flag is set to 1, if the lower byte of the
any computation is negative computation or comparison performed result contains even number of 1’s ; for
by an instruction is zero odd number of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Trap Flag
Over flow Flag If this flag is set, the processor enters
This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large
the single step execution mode by
enough to accommodate in a destination register. The result is of more than 7-bits
in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-
generating internal interrupts after the
bit sign operations, then the overflow will be set. execution of each instruction

Interrupt Flag
Direction Flag
This is used by string manipulation instructions. If this flag bit is ‘0’, the string
is processed beginning from the lowest address to the highest address, i.e., Causes the 8086 to recognize external mask
auto incrementing mode. Otherwise, the string is processed from the highest interrupts; clearing IF disables these
address towards the lowest address, i.e., auto incrementing mode. interrupts.
39
 Flag Register
Suppose we want to add two 16 bit numbers: A2C5H
and F2B1H
A2C5H = 1010 0010 1100 0101B Signed value= - 23867
16 Bit signed integer range:
-32,768 to +32,767
F2B1H = 1111 0010 1011 0001B Signed value= -3407

(+) 9576H= 1001 0101 0111 0110B Signed value= -27274

SF=1 CF=1 ZF=0 AF=0 PF=0 OF=0

40
 8086
Microprocessor Architecture

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

[Link]. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

41
 8086
Microprocessor Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to access memory
data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data) for string
operations
42
ADDRESSING MODES

46
 8086
Microprocessor Addressing Modes
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode 47

 8086
Microprocessor Addressing Modes
Group I : Addressing modes for
register and immediate data

1. Register Addressing The instruction will specify the name of the register which holds the
data to be operated by the instruction.
2. Immediate Addressing
Example:
3. Direct Addressing
MOV CL, DH
4. Register Indirect Addressing

5. Based Addressing The content of 8-bit register DH is moved to another 8-bit register CL

6. Indexed Addressing (CL)  (DH)

7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

48
 8086
Microprocessor Addressing Modes
Group I : Addressing modes for
register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit data is specified as
2. Immediate Addressing part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is moved to DL
6. Indexed Addressing
(DL)  08H
7. Based Index Addressing

8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is moved to AX
10. Indirect I/O port Addressing register

11. Relative Addressing (AX)  0A9FH

12. Implied Addressing

49
 8086
Microprocessor Addressing ModesGroup II : Addressing modes
for memory data

1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory location at which the
3. Direct Addressing
data operand is stored is given in the instruction.
4. Register Indirect Addressing
The effective address is just a 16-bit number written directly in the
5. Based Addressing instruction.

6. Indexed Addressing Example:

7. Based Index Addressing MOV BX, [1354H]

MOV BL, [0400H]
8. String Addressing
The square brackets around the 1354H denotes the contents of the
9. Direct I/O port Addressing
memory location. When executed, this instruction will copy the
10. Indirect I/O port Addressing contents of the memory location into BX register.

11. Relative Addressing This addressing mode is called direct because the displacement of
the operand from the segment base is specified directly in the
12. Implied Addressing instruction.

53
 8086
Microprocessor Addressing ModesGroup II : Addressing modes
for memory data

1. Register Addressing In Register indirect addressing, name of the register which holds the
effective address (EA) will be specified in the instruction.
2. Immediate Addressing
Registers used to hold EA are any of the following registers:
3. Direct Addressing
BX, BP, DI and SI.
4. Register Indirect Addressing
Content of the DS register is used for base address calculation.
5. Based Addressing
Example:
6. Indexed Addressing

7. Based Index Addressing MOV CX, [BX]

8. String Addressing Operations: Note : Register/ memory

enclosed in brackets refer to
9. Direct I/O port Addressing EA = (BX) content of register/ memory
BA = (DS) x 1610
10. Indirect I/O port Addressing MA = BA + EA
11. Relative Addressing (CX)  (MA) or,
12. Implied Addressing
(CL)  (MA)
(CH)  (MA +1)

54
 8086
Microprocessor Addressing ModesGroup II : Addressing modes
for memory data

1. Register Addressing In Based Addressing, BX or BP is used to hold the base value for
effective address and a signed 8-bit or unsigned 16-bit displacement
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing In case of 8-bit displacement, it is sign extended to 16-bit before

adding to the base value.
4. Register Indirect Addressing
When BX holds the base value of EA, 20-bit physical address is
5. Based Addressing calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is used.
7. Based Index Addressing
Example:
8. String Addressing
MOV AX, [BX + 08H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
0008H  08H (Sign extended)
11. Relative Addressing EA = (BX) + 0008H
BA = (DS) x 1610
12. Implied Addressing MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
(AH)  (MA + 1)
55
 8086
Microprocessor Addressing ModesGroup II : Addressing modes
for memory data

1. Register Addressing SI or DI register is used to hold an index value for memory data and
a signed 8-bit or unsigned 16-bit displacement will be specified in
2. Immediate Addressing the instruction.

3. Direct Addressing Displacement is added to the index value in SI or DI register to

obtain the EA.
4. Register Indirect Addressing
In case of 8-bit displacement, it is sign extended to 16-bit before
5. Based Addressing adding to the base value.
6. Indexed Addressing
Example:
7. Based Index Addressing

8. String Addressing MOV CX, [SI + 0A2H]

9. Direct I/O port Addressing Operations:

10. Indirect I/O port Addressing FFA2H  A2H (Sign extended)

11. Relative Addressing EA = (SI) + FFA2H

BA = (DS) x 1610
12. Implied Addressing MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
56
 8086
Microprocessor Addressing ModesGroup II : Addressing modes
for memory data

1. Register Addressing In Based Index Addressing, the effective address is computed from
the sum of a base register (BX or BP), an index register (SI or DI) and
2. Immediate Addressing a displacement.

3. Direct Addressing Example:

4. Register Indirect Addressing MOV DX, [BX + SI + 0AH]

5. Based Addressing Operations:

6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing
EA = (BX) + (SI) + 000AH
8. String Addressing BA = (DS) x 1610
MA = BA + EA
9. Direct I/O port Addressing
(DX)  (MA) or,
10. Indirect I/O port Addressing
(DL)  (MA)
11. Relative Addressing
(DH)  (MA + 1)
12. Implied Addressing

57
 8086
Microprocessor Addressing ModesGroup II : Addressing modes
for memory data

1. Register Addressing Employed in string operations to operate on string data.

2. Immediate Addressing The effective address (EA) of source data is stored in SI register and
the EA of destination is stored in DI register.
3. Direct Addressing
Segment register for calculating base address of
4. Register Indirect Addressing source data is DS and that of the destination data is ES

5. Based Addressing
Example: MOVS BYTE
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing Calculation of source memory location:

EA = (SI) BA = (DS) x 1610 MA = BA + EA
9. Direct I/O port Addressing
Calculation of destination memory location:
10. Indirect I/O port Addressing EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE

11. Relative Addressing

(MAE)  (MA)
12. Implied Addressing
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
Note : Effective address of the If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1
Extra segment register

58
 8086
Microprocessor Addressing Modes Group III : Addressing
modes for I/O ports

1. Register Addressing These addressing modes are used to access data from standard I/O
mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port address is directly
3. Direct Addressing specified in the instruction.

4. Register Indirect Addressing Example: IN AL, 09H

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing

7. Based Index Addressing Content of port with address 09H is

moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction will specify the
9. Direct I/O port Addressing name of the register which holds the port address. In 8086, the 16-
bit port address is stored in the DX register.
10. Indirect I/O port Addressing
Example: OUT DX, AX
11. Relative Addressing
Operations: PORTaddr = (DX)
12. Implied Addressing
(PORT)  (AX)

Content of AX is moved to port

whose address is specified by DX register.

59
 8086
Microprocessor Addressing Modes Group IV : Relative
Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of a program

instruction is specified relative to Instruction Pointer (IP) by an 8-bit
4. Register Indirect Addressing signed displacement.

5. Based Addressing Example: JZ 0AH

6. Indexed Addressing
Operations:
7. Based Index Addressing
000AH  0AH (sign extend)
8. String Addressing
If ZF = 1, then
9. Direct I/O port Addressing
EA = (IP) + 000AH
10. Indirect I/O port Addressing BA = (CS) x 1610
MA = BA + EA
11. Relative Addressing

12. Implied Addressing If ZF = 1, then the program control jumps to new address
calculated above.

If ZF = 0, then next instruction of the program is executed.

60
 8086
Microprocessor Addressing Modes Group IV : Implied
Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands. The instruction
itself will specify the data to be operated by the instruction.
7. Based Index Addressing

8. String Addressing Example: CLC

9. Direct I/O port Addressing This clears the carry flag to zero.

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

61
INSTRUCTION SET

62
 8086
Microprocessor Instruction Set

8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. Processor Control Instructions

5. Control Transfer Instructions

6. String manipulation Instructions

63
 8086
Microprocessor Instruction Set
1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.

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Microprocessor Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

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Microprocessor Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2

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Microprocessor Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, DX OUT DX, A

IN AL, DX PORTaddr = (DX) OUT DX, AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, DX PORTaddr = (DX) OUT DX, AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)
IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2)  (reg1) + (reg2)

ADD reg2, mem (reg2)  (reg2) + (mem)
ADD mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  Remainder

DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  Remainder

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  Remainder

IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  Remainder

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

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Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

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Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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Microprocessor Instruction Set
4. Processor Control Instructions
Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor which shares the
address and data bus with the 8086

LOCK Lock bus during next instruction 87

 8086
Microprocessor Instruction Set
5. Control Transfer Instructions

Transfer the control to a specific destination or target instruction

Do not affect flags

 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

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Microprocessor Instruction Set
5. Control Transfer Instructions
 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP

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Microprocessor Instruction Set
5. Control Transfer Instructions
 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or equal Jump if above Jump if not below or
equal
JGE disp8 JNL disp8
Jump if greater than or Jump if not less JAE disp8 JNB disp8
equal Jump if above or equal Jump if not below
JL disp8 JNGE disp8
Jump if less than Jump if not greater than JB disp8 JNAE disp8
or equal Jump if below Jump if not above or
equal
JLE disp8 JNG disp8
Jump if less than or Jump if not greater
equal
JBE disp8 JNA disp8
Jump if below or equal Jump if not above
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Microprocessor Instruction Set
5. Control Transfer Instructions

 8086 conditional branch instructions affecting individual

flags
Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

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Microprocessor Instruction Set
6. String Manipulation Instructions

 String : Sequence of bytes or words

 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.

 REP instruction prefix : used to repeat execution of string instructions

 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.

 Offset or effective address of the source operand is stored in SI register

and that of the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically

updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

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Microprocessor Instruction Set
6. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution of string instruction

Repeat while zero (ZF=1) and
(Repeat CMPS or SCAS until ZF = 0) (CX)  (CX) – 1

REPNZ/ REPNE
Repeat while not zero (ZF=0) While CX  0 and ZF = 0, repeat execution of string instruction
(Repeat CMPS or SCAS until ZF = 1) and
(CX)  (CX) - 1

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Microprocessor Instruction Set
6. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2

If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

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Microprocessor Instruction Set
6. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

CMPSW If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2
If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

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Microprocessor Instruction Set
6. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

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Microprocessor Instruction Set
6. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

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Microprocessor Instruction Set
6. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

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