Digital Design and

FPGAs
Module 5
Introduction to FPGA
• FPGA stands for Field-Programmable Gate Array.
• It is a reprogrammable digital chip that can be
configured by the user to perform any digital logic
function.
• It is a type of hardware that can be programmed after
manufacturing (in the “field”).
Role of FPGA
Immediate Availability:
• FPGAs can be programmed and tested immediately after design completion, eliminating
fabrication delays.

Excellent for Prototyping:

• FPGAs allow rapid prototyping and design validation before committing to expensive ASIC
fabrication.

Design Flexibility:
• The same FPGA device can be reprogrammed for multiple applications, reducing the need
for new hardware.

Reduced Inventory Costs:

• Since FPGAs are reusable, a single part can serve multiple designs, minimizing storage
and manufacturing expenses.
Role of FPGA
Fast Design-to-Product Transition:
• When used in final products, the shift from prototype to market-ready design is much
quicker and smoother.

Standard Component Advantage:

• Being standard parts, FPGAs are easily available and supported by mature design tools.

Supports Complex Logic Implementation:

• FPGAs overcome the limitations of older PLDs by using multi-level logic structures and
programmable interconnects.

Ideal for Rapid System Development:

• FPGAs enable engineers to test, modify, and optimize designs quickly—suiting dynamic
and evolving applications.
FPGAs and ASICs (Custom VLSI)
Definition:
• ASICs (Application-Specific Integrated Circuits) are designed for a fixed
function, while FPGAs (Field-Programmable Gate Arrays) can be
reprogrammed for different applications.

Design Flexibility:
• FPGAs are reconfigurable even after manufacturing, whereas ASICs
have fixed functionality once fabricated.

Design Time:
• FPGA designs can be implemented and tested within days, but ASICs
require months of design, fabrication, and testing.
FPGAs and ASICs (Custom VLSI)
Manufacturing Process:
• ASICs require custom masks and semiconductor
fabrication lines, making them time-consuming and
costly to produce.

Performance:
• ASICs generally offer higher speed and lower power
consumption compared to FPGAs, as they are optimized
for specific functions.
FPGAs and ASICs (Custom VLSI)
Cost:
• FPGAs have higher unit costs but no fabrication expenses, while
ASICs are cost-effective only when produced in large volumes.

Moore’s Law Impact:

• Increasing transistor density allows FPGAs to include millions of
transistors, enabling complex designs comparable to ASICs.

Development Risk:
• FPGA designs can be modified and tested easily, reducing risk; ASIC
errors, however, are costly to fix after fabrication.
FPGAs and ASICs (Custom VLSI)
Application Suitability:
• FPGAs are ideal for prototyping, research, and low-to-
medium volume production, while ASICs suit high-
volume, performance-critical products.

Industry Trend:
• Rising mask and fabrication costs have encouraged
many designers to adopt FPGAs for custom logic instead
of ASICs.
Advantages and disadvantages of
SRAM-based FPGAs
• Advantages of SRAM-based FPGAs

• Easy Reprogramming: Chips can be reused and reprogrammed without removal, making them ideal for
system prototyping.

• Dynamic Reconfiguration: Can be reprogrammed during system operation, enabling dynamically

reconfigurable systems.

• Standard Fabrication: Circuits can be fabricated using standard VLSI processes.

• No Refresh Needed: Unlike DRAM, SRAM does not require refreshing, simplifying configuration circuitry.

• Disadvantages of SRAM-based FPGAs

• High Power Consumption: SRAM configuration memory consumes noticeable power, even when unchanged.

• Security Risk: Configuration bits are susceptible to theft.

Architecture of FPGA Fabrics:
Methodology for
evaluating FPGA fabrics.
MetArchitecture of FPGA Fabrics:
Methodology for
evaluating FPGA fabrics.
Steps in the Evaluation Process
[Link] an FPGA Fabric:
Select a specific FPGA architecture (fabric) to be tested. The fabric includes the logic
blocks, interconnects, and routing resources.
[Link] Benchmark Designs:
Choose a set of representative logic circuits or benchmarks to test.
1. These benchmarks may come from customers, public design repositories, or previous studies.
2. They represent typical workloads or designs that users would implement on FPGAs.
[Link] the Benchmarks:
Use computer-aided design (CAD) tools to map, place, and route the benchmark designs
on the chosen FPGA fabric.
1. Placement: Assigns logic elements to physical locations.
2. Routing: Connects them using available interconnect resources.
[Link] the Metrics:
After implementation, measure several key performance parameters to assess the
quality of the FPGA design.
Interconnect Architecture
Interconnect Architecture in FPGAs – Key Points
[Link] Architecture vs. Circuit Design:
The interconnect architecture deals with how all the wires in an FPGA are arranged
and connected, while interconnect circuits deal with the design of drivers and
amplifiers for a single wire.
[Link] of Interconnects:
The interconnect system connects Logic Elements (LEs) together so that signals
can travel between different parts of the FPGA.
[Link] Basic Types of Connections:
To connect two LEs, three types of connections are needed:
1. From the logic element to the wiring channel
2. Between wire segments within the same channel
3. Between different wiring channels
[Link] Between Wire Segments:
Wires inside a channel can usually connect to adjacent wire segments to continue
the signal path.
Interconnect Architecture
[Link] vs. Cost:
More connection options (rich interconnects) give better routing flexibility but require
more programming circuitry, which increases cost and area.
[Link] Differences:
1. Antifuse-based FPGAs: Each logic element connects to one fixed wire in the channel.
2. SRAM-based FPGAs: Inputs and outputs can connect to multiple wires, giving more
flexibility.
[Link]-Channel Connections:
Ideally, crossbar switches could connect any wire from one channel to any wire in
another channel, but this is rare because it would require too much programming
circuitry.
[Link] Wiring:
FPGA wires are often divided into segments that span several LEs.
3. Longer segments reduce delay but connect to fewer points.
4. Offset wiring (staggered segments) ensures not all LEs connect to the same wires,
improving routing flexibility.
Four-input mux built from NAND
gates:
Four-input mux built from NAND gates:
•There are two select lines (S1, S0) and four data inputs (I0, I1, I2, I3).
•First, inverters (made from NANDs) create the complements of the select lines — S1' and
S0'.
•Each data input (I0–I3) goes into its own NAND gate along with the proper combination of
select signals.
•Example:
•I0 → with S1' and S0'
•I1 → with S1' and S0
•I2 → with S1 and S0'
•I3 → with S1 and S0
•The circuit uses NAND gates only to build the multiplexer.
•These NANDs decide which input is selected based on S1 and S0.
•The outputs of these NANDs are then combined by another NAND gate to produce the final
output.
•Only one input’s signal passes through, depending on the select values .
Rent’s Rule
• Pinout Importance: Determining the number of
pins is a key concern in FPGA design.
• Custom Design vs FPGA: In custom ICs, pin
count is based on the application; FPGAs provide
uncommitted logic, so pin planning differs.
• Excess Pins Issue: Too many pins increase the
chip package cost, which can be more expensive
than the chip itself.
• Insufficient Pins Issue: Too few pins limit the
ability to use all the logic available in the FPGA.
Rent’s Rule
• Rent’s Rule Formula
FPGA Types
• Key Characteristics
• Standard, General-Purpose Device
• FPGAs are not built for a specific function.
• They are manufactured as blank chips and programmed by the customer for a required
purpose.
• Implements Multi-Level Logic
• FPGAs can realize complex logic circuits with multiple levels of logic gates.
• This differs from PLDs (Programmable Logic Devices), which use only two levels of logic (such as
AND/OR or NAND/NOR).
• Programmable Logic and Interconnect
• FPGAs have two main programmable parts:
• Logic Blocks – implement the desired logical functions.
• Interconnects – connect these logic blocks together.
• PLDs, on the other hand, have fixed interconnects and only programmable logic.
• Fabric Structure
• The combination of programmable logic and interconnect forms a regular structure known as
the FPGA fabric.
• This fabric allows design tools to efficiently map user-designed logic onto the FPGA.
FPGA programming
FPGA programming
• FPGA Programmability – Key Points
• Main Feature:
• FPGA can be programmed by the user after manufacturing.
• FPGA vs Microprocessor:
• Microprocessor: Executes stored instructions (software).
• FPGA: Configuration defines hardware (logic + connections).
• FPGA does not fetch instructions; it directly performs logic functions.
• Programming Types:
• Permanent (one-time programmable) – cannot be changed.
• Reprogrammable (reconfigurable) – can be erased and reloaded.
• Reconfigurable FPGA Advantages:
• Useful for prototyping – no need to discard the chip after changes.
• Can be reprogrammed on-the-fly during operation.
• Enables multi-mode systems (e.g., display switching between portrait and landscape).
• Logic Granularity:
• Fine-grained FPGA: Small logic blocks (few gates + register).
• Coarse-grained FPGA: Larger blocks (e.g., ALU + register).
• Coarse-grained = better area efficiency for complex designs.
 FPGA
Architect
ures
FPGA architectures
• Basic Structure of an FPGA
• Main Elements:
• Logic Blocks (LEs/CLBs) – for logic functions.
• Programmable Interconnect – for routing connections.
• I/O Blocks (IOBs) – for external inputs and outputs.
• Logic Elements (LEs) / Combinational Logic Blocks (CLBs):
• Perform functions of several basic logic gates.
• Are small units compared to large circuit blocks in full designs.
• Programmable Interconnect:
• Connects LEs/CLBs together.
• Organized into channels or routing units.
• Offers different types of interconnects for short and long distances.
• Clock networks have dedicated routing paths.
• I/O Blocks (IOBs):
• Serve as programmable input/output pins.
• Can be set as input or output.
• Support features like high-speed or low-power operation.
Goals and Techniques in FPGA
Design
1. Performance
• The circuit must meet the required operating speed.
• Measured in terms of throughput, latency, or clock rate.
2. Power/Energy
• The design must stay within a defined power or energy budget.
• Essential for battery-powered systems and important for controlling heat
dissipation in grid-powered systems.
3. Design Time
• Fast design completion is crucial.
• FPGAs help reduce design time since they are:
• Standard parts (easily available)
• Quickly programmable
• Useful as prototypes for final ASIC designs.
Goals and Techniques in FPGA
Design
4. Design Cost
• Influenced by design time, tools, and resources used.
• FPGA tools are usually less expensive than custom
VLSI tools.
5. Manufacturing Cost
• Refers to the cost of replicating the system.
• FPGAs are generally costlier per unit than ASICs but
cheaper for small-scale or prototype production
due to no mask cost.
Design Challenges
[Link] Levels of Abstraction
[Link] must move from specification → architecture →
logic design through several refinement stages.
[Link] and Conflicting Costs
[Link]-offs exist between performance, power, and cost.
[Link] Design Time
[Link] market delivery is essential to reduce cost and
maximize profit.
[Link] products risk financial loss.
Hierarchical Design
Hierarchical Design
• Hierarchical design is a common method used to handle complex digital circuits by
breaking them into smaller, more manageable parts. This approach is similar to
programming, where large tasks are divided into smaller procedures. Each piece is
refined until it becomes simple enough to implement directly. This divide-and-
conquer method helps reduce complexity.
• Chip designers use hierarchy by organizing a circuit into components. A component
has a body and a set of pins. For example, a full adder has pins like a, b, cin, sum,
and cout as shown in figure.A component type defines its structure, and multiple
instances of the same type can be created (e.g., many full adders used to build an
n-bit adder). Each instance is given a unique name, and its pins are referred to using
the format [Link] (for example, [Link], [Link]).
• Designs often contain several components connected together. These connections
are made using nets, which act as wires between pins. In hierarchical diagrams,
each component is shown with its instance name and type name, along with the
nets that link their pins. This method allows designers to clearly represent and
organize the entire system while keeping the complexity under control.
How multiplexer can be used to
implement a logic element in an
FPGA?
• A multiplexer (MUX) can implement any logic function by
selecting one of several input values based on the input
variables.
• In many FPGAs, the basic logic element is built around a lookup
table (LUT), and a LUT internally behaves like a multiplexer. A k-
input LUT stores the truth table values for a logic function in
small memory cells. The input signals of the logic function act as
the select lines of a multiplexer.
• Based on the combination of these input bits, the MUX selects
one memory cell (which holds either 0 or 1) and produces it at
the output. This allows the LUT to generate any logic output for
those input combinations.
How multiplexer can be used to
implement a logic element in an
FPGA?
• In simple terms, the LUT works as a large multiplexer
where:The memory bits are MUX [Link] logic inputs
are MUX select [Link] MUX output gives the final
logic value.
• Thus, by using a MUX structure, an FPGA can implement
any combinational logic function, making the LUT a
flexible and universal logic element.