Chapter 1

Introduction to Field Programmable

Gate Arrays (FPGA)

Abstract In this chapter, the FPGA technology is introduced. First, the evolution
history of FPGA circuits and the fields of its application are reviewed. Then, an
overview of the basic FPGA architecture is presented. A comparison of the perfor-
mances between FPGA circuits and their ASIC counterparts is then established.
Finally, the whole design of FPGAs as well as the different steps required for the
design and the associated tools are described.

1.1 Introduction to FPGA

FPGAs (Field Programmable Gate Arrays) are semiconductor devices based on a

matrix of configurable logic blocks linked by programmable interconnections. Their
particularity comes from their re-configurability. FPGAs can be reprogrammed after
manufacture to meet the requirements of the desired applications or functionality.
The first commercial FPGA chip (XC2064) was introduced and delivered for
the first time in 1985 by the American technology company (Xilinx). This device
had a maximum capacity of 800 logic gates. The technology used was a 2 µm
aluminum technology with 2 levels of metallization. Xilinx will be followed a little
later, and never dropped, by its most serious competitor Altera which launched in
1992 the FPGA FLEX 8000. The maximum capacity reached 15,000 logic gates.
Taking advantage of the technological evolution, FPGA circuits have not stopped
developing and many manufacturers have since launched into the manufacture of
FPGAs (Xilinx, Altera, Actel, Latice, Motorola…). But the main manufacturers who
hold an important place on the market are Xilinx and Altera (Altera was absorbed in
2015 by Intel).
Since the 2000s, the complexity of FPGAs has reached 6.8 billion transistors, the
clock frequency exceeds one Gigahertz, and the most advanced technology today
reaches 16 nm (Xilinx Virtex UltraScale+).
Given their inherent configurability and relatively low development cost, the
impact of FPGA circuits on various engineering directions has grown with a rapid

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2022 3
B. Hajji et al., A Practical Guide for Simulation and FPGA Implementation
of Digital Design, Computer Architecture and Design Methodologies,
[Link]
4 1 Introduction to Field Programmable Gate Arrays (FPGA)

pace. FPGAs are useful for a wide range of applications, such as medical imaging,
aerospace and defense, automotive, video and image processing, etc.

1.2 FPGA Architecture

1.2.1 General Structure of an FPGA Circuit

An FPGA consists of a matrix of Configurable Logic Blocks (CLBs) surrounded by

input/output (I/O) blocks. The set of CLBs and I/Os is connected by routing resources
as depicted on Fig. 1.1.
The FPGA concept is based on the use of a LUT (Look-Up-Table) as a combi-
natorial element of the basic cell. This LUT can be seen as a memory that allows
creating any logic function. An N-input LUT consists of 2 N configuration bits into
which the required truth table is programmed during the configuration step. For area
and delay purposes, the optimal number of inputs for LUTs has been found to be
four. However, this number can vary depending on the targeted application by the
vendor. Table 1.1 lists some devices of the XILINX FPGA Virtex family with the

Fig. 1.1 Basic FPGA architecture

Table 1.1 XILINX FPGA

Family Year Technology Max cells
Virtex family with the
corresponding number of Virtex4 2004 90 nm 200,000 LUT4
LUT cells Virtex5 2007 65 nm 330,000 LUT6
Virtex6 2010 40 nm 760,000 LUT6
Virtex7 2012 28 nm 2,000,000 LUT6
1.2 FPGA Architecture 5

Fig. 1.2 Basic cell of an FPGA

corresponding number of LUT cells and the number of inputs for the LUTs. The
following figure (Fig. 1.2) represents a basic cell of an FPGA for a LUT of 4 inputs.
The D flip-flop allows the implementation of the function thanks to the memory
block. The configuration of the 2 to 1 output multiplexer allows the selection of the
two types of function: combinatorial or sequential.
The basic cells of an FPGA are arranged in rows and columns to form a Basic
Logic Element (BLE). The BLEs are grouped in turn to form the CLB a. Each
BLE can be connected to any input of the CLB or to another BLE as shown in
Fig. 1.3. The logic elements are connected to each other and to the I/O through the
interconnection network. This network is programmed in the same way as the logic
elements with static RAMs. The set allows to completely configuring the FPGA
whose CLB matrices can be organized from 8 × 8 to 128 × 128.
In addition to reconfigurable logic, contemporary FPGAs contain numerous
embedded blocks. Namely: Block RAMs used for efficient data storage and buffering.
Indeed, FPGAs are composed of memory blocks that allow configuring and freezing
the functionality of the circuit. There are several types of FPGAs (SRAM-based

(a) (b)

Fig. 1.3 a A configurable logic block b A basic logic element

6 1 Introduction to Field Programmable Gate Arrays (FPGA)

Fig. 1.4 Spartan-II XC2S15

device architecture overview

FPGAs, Flash-based FPGAs and Antifuse-based FPGAs), classified according to

the way they are programmed.
The majority of FPGAs use static memories. For example: Altera Cyclone II
offer between 119 and 1,152 Kbits of on-board memory and a global clock network
that includes 16 global clock lines driving the entire device. Xilinx Spartan-II (see
Fig. 1.4) also includes a fully Digital Delay-Locked loop (DLL) for clock distribution
delay compensation and clock domain control. It can eliminate the offset between
the clock input buffer and the internal clock input pins throughout the device.

1.2.2 FPGA Routing Architectures

The FPGA routing interconnect provides different connections between FPGA

components. Two types of interconnection topologies exist: Mesh and tree-based
interconnections (see Fig. 1.5). These architectures differ in the way that the logic
blocks are interconnected in the network.

[Link] Mesh Architecture

In the mesh architecture also called island style architecture, the CLBs are placed in a
2D grid organized in rows and columns and surrounded by interconnection resources
(Fig. 1.5a). Generally, the routing interconnects in mesh architecture is composed of
the following:
• Connection blocks responsible for connecting logical elements to the intercon-
nection network (Fig. 1.6a).
1.2 FPGA Architecture 7

(a) (b)
Fig. 1.5 a Mesh-based interconnect b tree-based interconnection

(a) (b)

Fig. 1.6 a Block de connection b switch bloc

• Switching blocks are used to connect all the connection blocks (Fig. 1.6b).
The number of connections between the switch blocks and the connection blocks
represents the routing channel of the FPGA. A routing channel is one of the most
important architectural parameters. Its size (the number of wires) must be set before
the manufacture of the FPGA by the designer and it must allow the routing of all the
signals of the application used by the FPGA.
The mesh architecture is the most common FPGA architecture used commercially.
However, 90% of the surface is occupied by the interconnection network, so the large
number of switches traversed increases considerably the propagation delay.

[Link] Tree-Based FPGA

In the tree architecture, the logical blocks are grouped in separate clusters and recur-
sively connected to form a hierarchical structure (Fig. 1.5b). Each cluster is composed
of a local interconnection network in the form of a switch box. Compared to the mesh
architecture, a connection between two logical blocks requires fewer switches. The
8 1 Introduction to Field Programmable Gate Arrays (FPGA)

number of switches in a tree architecture increases logarithmically in contrast to

the matrix architecture where the number of switches increases linearly with the
Manhattan distance between two logical blocks. However, in tree architecture, the
higher the number of levels in the architecture, the more difficult it is to generate the
corresponding layout. In addition, the mesh model is more scalable because it has a
regular structure that maximizes the use of the logic.

1.3 ASIC Versus FPGA Comparison

The ability to be reconfigured gives FPGA circuits’ great flexibility for use in
many designs. Their basic programming can be modified to make it specific to the
circuit being used or to improve or resolve faults, which is impossible with ASIC
(Application Specific Integrated Circuit) circuits.
An ASIC is a unique type of integrated circuit designed for a specific application
and cannot be modified once created. Indeed, designers need to be completely sure of
their design, especially if large quantities of the same ASIC are being manufactured.
With the programmable nature of an FPGA, manufacturers can correct design errors
and even send corrections or updates. This makes FPGAs ideal for prototyping.
Manufacturers can create their prototypes in an FPGA so that they can test and
revise them before moving to the production phase.
Another crucial advantage of FPGAs is their speed to market compared to ASICs.
Their design flow is extremely simple: one can test an idea or concept, and then verify
it on hardware without going through the long process of manufacturing an ASIC.
Once the program is validated, it takes only a few minutes to implement.
Due to the above-mentioned advantages of FPGAs, they are constantly increasing
their market share compared to ASICs. Although ASICs are generally less expensive
than an FPGA solution, FPGAs are a worthwhile investment in the long term. This
is due to their re-programmability and flexibility, which means they can be reused
for other projects, despite the higher purchase price of an ASIC. However, the main
advantage of FPGAs, namely their flexibility, is also the main cause of their disad-
vantage. The flexible nature of FPGAs makes them larger, slower and more power
consumption than their ASIC counterparts. An FPGA requires 20 to 35 times more
area, and a speed 3 to 4 times slower than the ASIC. Table 1.2 summarizes the main
differences between FPGAs and ASICs.

Table 1.2 ASIC versus

FPGA ASIC
FPGA comparison
Time to market Fast Slow
Design flow Simple Complex
Unit cost High Low
Power consumption High Low
Unit size Medium Low
1.4 Design Methodology 9

1.4 Design Methodology

The FPGA design flow consists of different phases, as shown in the figure below
(See Fig. 1.7). Each phase will be explored in detail in the following.

1.4.1 Design Entry

The design entry can be accomplished by two methods:

• Use of a schematic: the design is carried out with the help of gates and wires.
Indeed, it is easily readable, understandable and they offer a better visibility of
the whole system. But for large designs become difficult to maintain.
• Use of Hardware Description Language (HDL): a fast language-based process that
avoids the need to design lower-level hardware. It is more suitable for complex
systems and is the most popular design input for FPGA designs. Two languages
those are popular for FPGA designers: VHDL and Verilog (more discussed in
Chap. 2).
Once the desired functionality of the circuit or system to be designed is specified,
its behaviour can be modelled through functional simulation. This means that the
circuit can be tested to verify its operation. If a problem is detected, the necessary
changes are made to the circuit specification.

1.4.2 Synthesis

Once the design has been simulated correctly, we move on to circuit synthesis. A
logic synthesis converts the design input into a netlist of basic logic gates such as
LUTs, flip-flops, memories, DSP slices, etc. This phase usually goes through two
different steps: logic optimization and technology mapping.
Logic optimization consists in simplifying the logic function of the design or
any redundant logic is removed at this stage. The optimized circuit is then mapped
while taking into consideration the speed, area or power constraints imposed by the
designer.
FPGA synthesis is performed by dedicated synthesis tools such as: Cadence,
Synopsys and Mentor Graphics.
10 1 Introduction to Field Programmable Gate Arrays (FPGA)

1.4.3 Implementation and Programming

This phase consists of three steps: translate, map, and place & route. The first step
consists of converting the input netlist into clusters of logic blocks that can be mapped
into the physical logic blocks of the FPGA (Fig. 1.8). In the place phase, the encap-
sulation algorithm used must take into account all user-defined constraints, namely:
pin assignment and position, timing requirements such as maximum delay or clock
input period.
The next step is to allocate the available routing resources in the FPGA to the
different connections between all logic blocks and I/O blocks. The routing algorithm
in this phase should minimize the delay along the critical path and avoid congestion
in the FPGA routing resources.
The placement and routing tools used in this step are provided by the FPGA
vendors. At the output, a “Bitstream” file is provided that can be downloaded to the
FPGA device.
The final step in the process is to upload the generated “Bitstream” file to the
FPGA. Then, the resulting physical circuit undergoes final in-circuit testing.

1.4.4 Design Tools

To complete the design process, from circuit specification to simulation, synthesis

and implementation, a CAD tool is used. At each stage, the CAD environment allows
for simulations to be performed in order to validate each step of the implementation.
At design entry, a behavioral simulation is performed to test the code and find logical
errors. At synthesis, the functionality of the design can be verified using a functional
simulation that ignores timing issues. At implementation, a simulation is performed
to check timing performance, device resource usage, and power consumption. It takes
more time and provides much more detail than previous simulations. The results of
this simulation may require the designer to go back and make changes to the circuit
specification, design constraints, or synthesis strategies.
In this book, we will mainly use ISE version 14.7 for Xilinx FPGAs and Quartus
II 13 for Altera FPGAs. Moreover, a range of CAD tools is offered by both Xilinx
and Intel and can also be used in a similar way. The underlying ideas are exactly the
same, only the corresponding software environments are different.
To summarize the design flow shown in Fig. 1.7, consider all of the steps that
must be completed in Quartus in order to implement a “xor” gate:
• Creation of a project

We start by creating a new project (file > new project wizard) by specifying its
name, location and the name of the top-level entity (see Fig. 1.9). Please note that
the name of the project and the name of the top-level entity must be the same.
Then the characteristics of the target FPGA are selected (see Fig. 1.10). In our case,
1.4 Design Methodology 11

Fig. 1.7 Simplified FPGA design flow

we have selected “Cyclone II” as the FPGA family and also indicated the device
EP2C70F896C6. These data can be found in the documentation that accompanies
the device and are also written on the appropriate chip.
• Circuit description
Once the project is created, the circuit can be described. In the “FILE” menu, we
choose “NEW”. Window offering different types of description appears. Since we
are interested in VHDL language, we choose “VHDL File” (see Fig. 1.11) and we
write the VHDL code in the dedicated area. The VHDL code can also be edited in
any text editor except that it must be saved with the extension (.vhd) and added to
the project (Project > add/Remove file in Project).
12 1 Introduction to Field Programmable Gate Arrays (FPGA)

Fig. 1.8 An example of cluster packing

Fig. 1.9 Creation of new project under Quartus II

• Compiling the program

After saving the VHDL code in the project directory and with the same name as
the Entity, the code can be compiled (processing > start compilation). The compiler
generates a report indicating all errors and / or warnings found, as shown in Fig. 1.12.
1.4 Design Methodology 13

Fig. 1.10 Choice of device family under Quartus II

Once the compilation is finished without any indication of errors, the description
is synthesizable in a layout that can be viewed on the menu: “Tools > NETlist Viewers
> RTL Viewer” (see Fig. 1.13).
• Pin assignment
At the next step, I/O of the circuit described are assigned to the pins of the used
FPGA device (Assignment > pin planner). At pin planner, the different nodes with
their direction (Input/output) are listed. We choose the appropriate location of each
node. In our case, the inputs take the addresses of two switches (PIN_N25, PIN_P25)
and the output takes the address of an LED (PIN_AE23) on the FPGA board (see
Fig. 1.14).
• Functional Simulation
To perform a simulation, the test vectors must be defined on the menu: File > New
> Vector Waveform (see Fig. 1.15).
First, we introduce the I/O of the circuit by going to the menu: Edit > Insert > Insert
Node or Bus. The window of Fig. 1.16 is displayed. By clicking on “node finder”
another window is displayed where the different available nodes are listed. Just select
the desired node for the simulation and transfer it to the right tab (Fig. 1.16).
14 1 Introduction to Field Programmable Gate Arrays (FPGA)

Fig. 1.11 Choice of language Quartus II description under

Fig. 1.12 Compilation report

1.4 Design Methodology 15

Fig. 1.13 Synthesizable layout after compilation

Fig. 1.14 Pin planner for assignment

Once the I/O are on the editor window, we define the test vectors by drawing up
a chronogram and specifying the simulation time (Edit > End Time) (see Fig. 1.17).
Finally, the simulation can be executed by going to the: Processing > Simulator
tool menu > Functional simulation mode. Then, we go to the Processing > Generate
Functional Simulation Netlist > start.
The results of simulation are shown on Fig. 1.18.
16 1 Introduction to Field Programmable Gate Arrays (FPGA)

Fig. 1.15 Vector waveform

of Qartus II

Fig. 1.16 Node insertion in

Qartus II
1.4 Design Methodology 17

Fig. 1.17 Test vectors before simulation under Qartus II

Fig. 1.18 Simulation results under Qartus II

• Programming and configuration of the FPGA circuit

The final step is to transfer the program to the FPGA board; we start in the “Tools
> Programme” menu, then the window below appears. By clicking on “start” the
program is transferred to the card while viewing the progress of the transfer (see
Fig. 1.19).

Fig. 1.19 Programming step under Qartus II

18 1 Introduction to Field Programmable Gate Arrays (FPGA)

1.5 Summary

A brief overview of the different aspects related to FPGAs is presented in this chapter.
In summary:
• An FPGA circuit is a flexible solution well adapted to economic constraints.
Reduced time to market with performance and capabilities to integrate very
complex applications.
• The internal architecture of FPGAs differs from one manufacturer to another
and even between the different ranges of the same manufacturer. Generally, it is
composed of a matrix of configurable logic blocks surrounded by input and output
blocks.
• Design and simulation are the two main steps in the design flow of an FPGA.
The design tasks allow going from one description to another to arrive at the
configuration “bitstream”file.
• At each stage of the design process, the CAD environment allows simulations to
be carried out in order to validate each stage of the implementation.