Intra/Inter Institutional Internship-1

Internship report submitted in partial fulfillment of the

completion

Bachelor of Engineering

in

ELECTRONICS & INSTRUMENTATION ENGINEERING

of

Visvesvaraya Technological University, Belagavi

by
Student Name: GOWTHAMI JAIN
USN : 1SI21EI016

Department of Electronics & Instrumentation

Engineering SIDDAGANGA INSTITUTE OF
TECHNOLOGY TUMAKURU-572103
2022-23

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 SIDDAGANGA INSTITUTE OF TECHNOLOGY
TUMAKURU-572103
(An Autonomous Institute Affiliated to Visvesvaraya Technological University, Recognized by AICTE,
Accredited by NBA, New Delhi, NAAC with ‘A’ Grade & ISO Certified)
Department of Electronics & Instrumentation Engineering

Certificate
Certified that the project work entitled

Intra/Inter Institutional Internship-1

is a bonafide work carried out by

GOWTHAMI JAIN

in partial fulfillment for the completion of Intra/Inter Institutional Internship of Degree of

Bachelor of Engineering in Electronics & Instrumentation Engineering of the
Visvesvaraya Technological University, Belagavi during the year 2022-2023. It is
certified that all corrections /suggestions indicated for internal assessment have been
incorporated in the report deposited in the Department.

Proctor Head of the Department

Name of the Student: GOWTHAMI JAIN

University seat number: 1SI21EI016

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 ACKNOWLEDGEMENT

We are delighted to express our sincere gratitude and pranaam to his Holiness the late and
lamented Dr. SREE SREE SHIVAKUMARA SWAMIGALU, Founder President and
his holiness,SREE SREE SIDDALINGA SWAMIGALU, President, Sree Siddaganga
Education Society, Sree Siddganga Mutt for all their blessings bestowed upon us, which
has been a constant and immense blessing during our course of study.

We duly respect and thank our respected Director Dr. [Link], for his
sincere dedication, perseverance for creating a continuous platform towards the society
and betterment of the nation in the field of education, as the future of every nation lies in
the hands of education.

We express our gratitude and will remain indebted to Dr. Shivakumariah, C.E.O and
[Link], Principal, SIT, Tumakuru, for fostering an excellent academic
environment in this institution and also providing excellent campus facilities, which made
our endeavor possible.

We are grateful to Dr. H M Kalpana, Professor and Head, Department of E&IE, SIT for
continuous support and encouragement. Her suggestions and advice have been valuable.

We would like to thank all the faculty members and supporting staff of our department
for their encouragement and also our parents and friends for their immense support and
encouragement throughout this journey.

GOWTHAMI JAIN

1SI21EI016

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CONTENTS

List of figures
List of tables
Chapter Title Page no.
1. INTRODUCTION 1
2. MULTISIM (MAT) 1-11
2.1 Day-1 (All Sessions details)
12-18
2.2 Day-2 (All Sessions details)
19-34
2.3 Day-3 (All Sessions details)

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INTRODUCTION

CHAPTER 1
INTRODUCTION ABOUT LOGIC GATES AND TTL

LOGIC GATES:

A logic gate performs a logical operation on one or more logic inputs

and produces a single output.
TTL:TRANSISTOR TO TRANSISTOR LOGIC
The TTL is a logic family made up of BJT’s (bi-polar junction
transistor)as the name suggests the transistor performs two
functions like logic as well as amplifying.
ADVANTAGES :
[Link] power dissipation when compare to RTL.
[Link] cost, faster, high reliability.
[Link] to interface several circuits.
DISADVANTAGE:
[Link] suitable for high end electronic device.
APPLICATION:
[Link] and microprocessors.
[Link] circuits.
[Link] and low power electronics devices.

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AIM: To verify the truth table of NAND gate.
THEORY: An AND gate coupled with a NOT gate performs the NAND gate is low
if all the inputs are low or the output of is high if any of the output is high.
APPLICATION: Used in alarm circuits through light detection radiation.
[Link] gate are utilized in automatic temperature regulation circuits.
CIRCUIT DIAGRAM:

U3 X1
0
Key = Space U1A 2.5V

U2 7400N
0
Key = Space

TRUTH TABLE:
A B Y=A.B Y=A’.B’
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0

REPORT: The truth table of NAND GATE is verified.

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AIM: To verify the truth table of NOR gate.

THEORY: The OR gate coupled with a NOT gate performs the NOR operation
the output of a NOR gate is high if all the inputs are low or if any of the inputs
are high the output of a NOR gate is low.
APPLICATIONS: These are used in combinational circuits such as multipliers,
half and full adder.
CIRCUIT DIAGRAM:
X1
U2
1
U1A 2.5V
Key = Space

U3 7432N
1
Key = Space

TRUTH TABLE:

A B Y=A+B Y=A’+B’
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0

RESULT: The truth table of NOR GATE is verified.

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AIM: To verify the truth table for OR gate.
THEORY :An OR gate can have two or more inputs and one output.
In OR gate if all the inputs are low output will be low and if any one input is
high.
APPLICATION: These are used in circuits where various power sources are
available to perform the similar action.
[Link] in industrial plants for some protective measures.
U2
X1
0
Key = Space
U1A 2.5 V

7402N
U3
0
CIRCUIT DIAGRAM: Key = Space

TRUTH TABLE:
A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 1

RESULT: The truth table of OR GATE is verified.

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AIM: To verify the truth table of INVERTER GATE.
THEORY: Inverter will have one input and one output in NOT gate is the output
is always complement of input.
APPLICATION: Employed in temperature detection devices.
[Link] in crystal oscillator.
CIRCUIT DIAGRAM:
X1

U1A 2.5V
U2
1
Key = Space 7404N

TRUTH TABLE:
A Y=A’
0 1
1 0

RESULT: The truth table of inverter gate is verified.

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AIM: To verify the truth table of AND gate.
THEORY: An AND gate has two or more inputs and one [Link] AND gate if
all the inputs are high output will be high and if any one input or all the inputs
are low outputs will be low.
APPLICATION: Used in digital measuring devices, alarm circuits.
[Link] warming buzzer devices.
CIRCUIT DIAGRAM:
X1

U2
2.5V
1 U1A
Key = Space
U3 7408N
1
Key = Space

TRUTH TABLE:
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

REPORT: The truth table of AND GATE is verified.

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AIM: To verify the truth table of XOR gate.
THEORY: An XOR gate will have two or more inputs and one output .In a two
Inputs are exclusive to each other the output will be high and if inputs are of
same logic the output will be low.
In an input XOR gate ,if ODD number of inputs the output will be high and if
the number of inputs are high output will be low.
X1
U2
1 2.5 V
Key = Space U1A

U3
0 7486N

CIRCUIT DIAGRAM: Key = Space

TRUTH TABLE:
A B A⊕B

0 0 0
0 1 1
1 0 1
1 1 1

REPORT: The truth table of XOR GATE is verified.

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AIM: To realize the circuit for the following Boolean expressions and verify the
truth table.

Theory : Here the two inputs A and B are connected to AND gate .
[Link] C and D input are connected to another AND gate.
[Link] and CD are connected to OR gate .
[Link] truth table are verified for 4 inputs .

EXPRESSION:
Z=AB+CD

CIRCUIT DIAGRAM:
U4
0
X1
Key = Space
U1A
2.5V
U5
0 7408N
Key = Space
U3A

U6 7432N
1
Key = Space
U2B

U7 7408N
1
Key = Space

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TRUTH TABLE :
A B C D AB CD AB+CD
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 0 1 1
0 1 0 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 0 0 0
0 1 1 1 0 1 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 0 1 1 0 1 1
1 1 0 0 1 0 1
1 1 0 1 0 1 1
1 1 1 0 1 0 1
1 1 1 1 1 1 1

REPORT : The truth table of the Boolean expression is verified.

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AIM: To realise and verify the truth table of boolean expression.
THEORY: Here the A is inverted to A’ and similarly B is inverted to B’ and
connected to AND gate .
C and D are connected to OR gate.
A’B’ and C’D’ are together connected to AND gate.
EXPRESSION:
Z=A’B’(C+D)
CIRCUIT DIAGRAM :
U5 U1A
0
Key = Space U3A X1
U6 7404N
U2B
0 7408N 2.5 V
Key = Space U9A
7404N
U7
0 7408N
Key = Space U4A
U8
1 7432N
Key = Space

A B C D A’B’ C+D A’B’(C+D)

0 0 0 0 1 0 0
0 0 0 1 1 1 1
0 0 1 0 1 1 1
0 0 1 1 1 1 1
0 1 0 0 0 0 0
0 1 0 1 0 1 0
0 1 1 0 0 1 0
0 1 1 1 0 0 0
1 0 0 0 0 1 0
1 0 0 1 0 1 0
1 0 1 0 0 1 0
1 0 1 1 0 0 0
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 1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 0 1 0
1 1 1 0 0 1 0
TRUTH TABLE:

REPORT: The truth table of the Boolean expression is verified

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AIM: To realise and verify the truth table of Boolean expression .
THEORY: First the three inputs are connected to 3 input AND gate.
B and C are inverted to B’ and C’ and together connected to OR gate then Ais
joined to B’ and C’.
Then all together connected to OR gate .

EXPRESSION :
Z=ABC+A(B’+C’)

CIRCUIT DIAGRAM :

Key = Space
U7
0

U8
0
Key = Space U1A
U9
0
Key = Space 74LS11N X1

2.5V
U6A

7432N
U10
1
Key = Space
U5A
U11 U2A
1
Key = Space 7408J
7404N U4A

U12 U3B 7432N

0
Key = Space 7404N

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TRUTH TABLE :
A B C B’ C’ ABC A(B’+C’) ABC+A(B’+C’)
0 0 0 1 1 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 1 0 0 0
0 1 1 0 0 0 0 0
1 0 0 1 1 0 1 1
1 0 1 1 0 0 1 1
1 1 0 0 1 0 1 1
1 1 1 0 0 1 1 1

REPORT : The truth table of the Boolean expression is verified

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AIM : To verify the truth table of boolean expression .
Theory :
1. First the 3 inputs are connected to 3 input AND gate .
2. Band C ARE INVERTED TO B’ AND C’ and together connected to OR gate then A’ is
joined to B’ and C’
3. Then all together connected to OR gate .
4. Finally verified the TRUTH TABLE.

EXPRESSION :
Z=ABC+DE.
CIRCUIT DIAGRAM :

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TRUTH TABLE :
A B C D E ABC DE ABC+DE
0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
0 0 0 1 1 0 1 1
0 0 1 0 0 0 0 0
0 0 1 0 1 0 0 0
0 0 1 1 0 0 0 0
0 0 1 1 1 0 1 1
0 1 0 0 0 0 0 0
0 1 0 0 1 0 0 0
0 1 0 1 0 0 0 0
0 1 0 1 1 0 1 1
0 1 1 0 0 0 0 0
0 1 1 0 1 0 0 0
0 1 1 1 0 0 0 0
0 1 1 1 1 0 1 1
1 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0
1 0 0 1 0 0 0 0
1 0 0 1 1 0 1 1
1 0 1 0 0 0 0 0
1 0 1 0 1 0 0 0
1 0 1 1 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 0 0 0 0 0
1 1 0 0 1 0 0 0
1 1 0 1 0 0 0 0
1 1 0 1 1 0 1 1
1 1 1 0 0 0 0 0
1 1 1 0 1 1 0 0
1 1 1 1 0 1 0 0
1 1 1 1 1 1 1 1

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FULL ADDER :
AIM: To realise half adder using basic gates and NAND gate and verify the truth
table .
THEORY : A half adder can add only two bits at a time hence it can be used
only to add 2 least significant bits of two multi bit number .For adding bits in
any other position the carry is generated in previous bit stage need to be
considered hence an adder that can add there bits is needed such an adder is
called FULL ADDER.
APPLICATION:
Full adder are mainly used for multipliers bit addition in digital processing
devices.
2. Full adders are useful in ALU (arithematic logic unit ) systems.

EXPRESSION:
SUM :A⊕B⊕Cin
CARRY : A Cin + B Cin + A B

CIRCUIT DIAGRAM :
FULL ADDER USING BASIC GATES :
B
U10
1
Key = Space U2B
U6B X1

7400N 2.5V
7400N
U4D U5A U7C
U1A

U11 7400N 7400N 7400N

7400N
1 U8D
Key = Space U3C
7400N

7400N X2

U12
U9A 2.5V
1
Key = Space
7400N

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 X1

U6
U3B 2.5 V
1 U1A
Key = Space
X2
74136N
U7 74136N
U5A 2.5 V
1 U2A
Key = Space U4B

7432N
7408J
U8 7408N
1
Key = Space

FULL ADDER USING NAND GATE

TRUTH TABLE :
A B Cin SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

REPORT : The truth table of FULL ADDER is verified .

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HALF ADDER :
Aim : To realise the HALF ADDER using basic gate and using NAND gate .
THEORY :Half adder is a logic circuit which arithematically adds two binary bits
A and B and generate SUM and CARRY .
APPLICATIONS : [Link] adder circuits are used in computer ,calculators and
various digital measuring instruments .
2.A half adder is used for adding together the two least significant bits in a
binary sum .
EXPRESSION :
SUM :A’B +AB’
CARRY : A.B
CIRCUIT DIAGRAM :
U5 U1A U7C X1
0
Key = Space 7404N 7408N U4A 2.5 V
U6
1 7432N
Key = Space U1B
U3B

7404N X2
7408N

2.5 V
U7A

7408N T
RUTH TABLE :
A B SUM CARRY
0 0 1 0
0 1 0 0
1 0 1 0
1 1 0 1
REPORT : The truth table of half adder using both NAND and BASIC gates is
verified

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FULL WAVE RECTIFIER :
AIM :To plot the characteristic of full wave rectifier .
THEORY : Since the flow of current in the load during both positive half cycle
and negative half cycle is in the same direction , the negative half cycle of the
same direction ,the negative half cycle of the input will be inverted at the
output hence a bidirectional signal will be converted to unidirectional signal .
CIRCUIT DIAGRAM :

FULL WAVE RECTIFIER CIRCUIT :

XSC1

Ext Trig
+
_
A B D1
+ _ + _
T1
V1
120Vrms 1N4007
60Hz
0°
R1

50Ω

D2

[Link]
1N4007

REPORT : The characteristics of FULL WAVE RECTIFIER is verified.

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AIM : To plot the characteristics of BJT the CE configuration .
THEORY :DC load line is a straight line drawn on output characteristics of CE
configuration which will hive all possible operating points of a transistors for
the given parameters of a transistor circuit .
CE CONFIGURATION AND CHARACTERISTICS OF BJT :

XIV1

R2

1kΩ
R1

1kΩ Q1 V2
V1 BC548A 12V
12V

GRAPH :
REPORT :The characteristics of BJT is verified.

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AIM : To plot the voltage -current characteristics of PN junction diode .
THEORY :The V-I characteristics of a diode is the plot of voltage across the
device and current through the device in both forward and reverse biased
condition .Forward biased condition until cut in voltage a small current will
flow across the diode and when the applied voltage is increased beyond the
cut in voltage forward current increases exponentially in the diode offering low
resistance. In reverse biased condition a small current will flow through the
diode due to minority charge carriers offering very high resistance when the
applied voltage is increased to greater extent avalanche breakdown take place.

CIRCUIT DIAGRAM :
CIRCUIT OF FORWARD BIAS P-N JUNCTION:

XMM1
XMM2

D1

1N4007

V1 R1
0V 5Ω
Key = A

OUTPUT OF FORWARD BIASED PN JUNCTION :

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CIRCUIT OF THE REVERSE BIAS:

OUTPUT OF REVERSE BIASED PN JUNCTION :

TABULAR COLUMN :
FORWARD BIAS :
INPUT VOLTAGE OUTPUT VOLTAGE CURRENT IN
IN mv IN mv µA
0.1 99.99 189.18n
0.2 199.93 1.496
0.3 299.947 10.518
0.4 399.638 72.44
0.5 497.594 481.27
0.6 586.58 2.68m
0.7 652.38 9.523m
0.8 694.19 21.162m
0.9 721.78 35.64m
1.0 741.67 51.66m

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REVERSE BIAS
VOLTAGE I/P OUTPUT CURRENT IN
VOLTAGE IN mV nA
0.1 100 27.458
0.2 200 31.517
0.3 300 32.19
0.4 400 32.37
0.5 500 32.48
0.6 600 32.58
0.7 700 32.68
0.8 800 32.78
0.9 900 32.88
1.0 1V 32.98

Graph of PN JUNCTION:

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ZENER DIODE :
AIM :To plot the V-I characteristics of Zener diode.
THEORY :Zener diodes are usually heavily doped diodes hance the depletion layer is very
narrow when the reverse voltage across the junction is increased the electric field voltage
across the depletion layer becomes high so that electrons are oulled out of covalent bonds
resulting in a sudden rise in current which is known as ZENER BREAKDOWN .
The forward biased characteristics of Zener diode is similar to that of conventional PN
junction ,whereas in reverse biased condition the Zener diode will conduct at Zener
breakdown voltage Vz.

CIRCUIT DIAGRAM :

TABULAR COLUMN :
FORWARD BAIS:
VOLTAGE IN VOLTS CURRENT IN mA
0 0
0.1 10
0.2 20
0.3 30
0.4 40
0.5 50
0.6 60
0.7 70
0.8 80

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AIM :To verify the kirchoff’s voltage law (KVL).
THEORY :The algebraic sum of voltage drop in the resistor across the closed
path is zero .
CIRCUIT DIAGRAM :
XMM1

R1 XMM2

1kΩ

V1 R2
12V 2kΩ

R3

3kΩ

XMM3

OUTPUT OF KVL :

REPORT : The kirchoff’s voltage law is verified.

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AIM :To verify the kichoff’s current law (KCL) .
THEORY : The algebraic sum of current meeting at a junction is equal to zero .
Sum of current entering the junction is equal to current leaving the junction .
CIRCUIT DIAGRAM :

OUTPUT OF KIRCHOFF ‘S CURRENT :

REPORT : The kirchoff’s current law is verified.

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AIM :To verify the OHM ‘S LAW.
THEORY : “THE CURRENT FLOWING THROUGH THE CONDUCTOR IS DIRECTLY
PROPORTIONAL TO THE POTENTIAL DIFFERENCE BETWEEN THE ENDS OF THE
CONDUCTOR KEEPING THE TEMPERATURE CONSTANT .”
EXPRESSION : V=IR
CIRCUIT DIAGRAM :
R1

1kΩ
V1
7V
Key = A XMM1

OUTPUT OF THE OHM’S LAW :

GRAPH :

REPORT :The OHM’S LAW is verified.

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AIM :To implement the ADDER circuit .
THEORY :The op-amp non inverting .the input signal is applied to the non inverting input
terminal the non inverting amplifier will amplify the input signal and the output signal will
be inphase with the input signal.

CIRCUIT DIAGRAM :
VCC XMM1
10V

U1

7
5
1
3
6
2

R1 741
4

1kΩ
V1 VEE
1.8V -10V
Key = A R2

1kΩ R3

V2 25kΩ
1.8V
Key = A

OUTPUT OF THE ADDER :

REPORT :Adder circuit is verified.

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AIM :To implement the inverting amplifier with gain of 10 .
THEORY :The OP -AMP inverting amplifier ,the input signal is applied to the
inverting terminal and the non-inverting input terminal is grounded .The
inverting amplifier will amplify the input signal and the output signal will be
180deg out of phase with the input signal and the output .
-sing indicates output is 180deg out of phase with input .
EXPRESSION : AV =-RF/R1
CIRCUIT DIAGRAM :

OUTPUT OF INVERTING AMPLIFIER :

REPORT :The inverting amplifier is verified.

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AIM :To implement the non-inverting amplifier with gain 11.
THEORY :THE op-amp non-inverting amplifier ,the input signal is applied to the
non-inverting input terminal the non-inverting amplifier will amplify the input
signal and the output signal will be inphase with the input signal .
CIRCUIT DIAGRAM :

OUTPUT OF NON-INVERTING AMPLIFIER:

REPORT :The NON -INVERTING AMPLIFIER is verified.

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AIM :To implement the voltage follower .
THEORY :The op-amp voltage follower ,the input signal is applied to the non-
inverting input terminal and inverting input terminal is connected to the
output terminal.
Output follows the input signal ,hence the name voltage follower.
CIRCUIT DIAGRAM :

XMM1
VCC
12V

U1
7
5
1

3
6
2

V1
7V 741
4

Key = A

VEE
-12V

OUTPUT OF VOLTAGE FOLLOWER :

Report :
THE VOLTAGE FOLLOWER IS VERIFIED.

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