Analysis and design of
Combinational logic
Half adder
Full adder
Full adder using half adder
Sum = A ⊕ B ⊕ C
Carry = AB + (A ⊕ B)C
= AB + (A’B + AB’)C
= AB + A’BC + AB’C
= B (A + A’C) + AB’C
= B [(A + A’)(A + C)] + AB’C
= AB + BC + AB’C
= BC + A(B + B’C)
= BC + A[(B + B’)(B + C)]
= BC + AB + AC
= AB + BC + AC
Binary Subtractor
4-bit ripple carry adder
1 1 0 0 0
4-bit ripple carry adder/Parallel adder
C3 = Cout
Working of Ripple Carry Adder /Parallel adder
• Firstly the Full Adder A adds A0 and B0 along with the carry Cin to
generate the sum S0 (the first bit of the output sum) and the carry
C0 which is connected to the next adder in chain.
• Next, the Full Adder B uses this carry bit C0 to add with the input
bits A1 and B1 to generate the sum S1(the second bit of the
output sum) and the carry C1 which is again further connected to
the next adder in chain and so on.
• The process continues till the last Full Adder D uses the carry bit
C2 to add with its input A3 and B3 to generate the last bit of the
output S3 along with last carry bit C3.
Parallel Subtractor
Working of Parallel Subtractor
• The parallel binary subtractor is formed by combination of all full
adders with subtrahend complement input.
• This operation considers that the addition of minuend along with
the 2’s complement of the subtrahend is equal to their subtraction.
• Firstly the 1’s complement of B is obtained by the NOT gate and 1
can be added through the carry to find out the 2’s complement of
B. This is further added to A to carry out the arithmetic subtraction.
• The process continues till the last full adder uses the carry bit to
add with its input A and 2’s complement of B to generate the last
bit of the output S3 along last carry bit C4.
For Subtraction
For a>b, a=b
• If a carry is generated (C4=1) , then ignore the carry
and result will be the difference between a and b.
For a<b
• If no carry (C4=0), then the difference is 2’s
compliment of the result with negative sign
Parallel Adder and Subtractor
• In Digital Circuits, A Binary Adder-Subtractor is capable of
both the addition and subtraction of binary numbers in one
circuit itself. The operation is performed depending on the
binary value the control signal holds. It is one of the
components of the ALU (Arithmetic Logic Unit).
• Let’s consider two 4-bit binary numbers A and B as inputs to
the Digital Circuit for the operation with digits
a3 a2 a1 a0
b3 b2 b1 b0
• The circuit consists of 4 full adders since we are performing
operations on 4-bit numbers. There is a control line C0 that
holds a binary value of either 0 or 1 which determines that the
operation is carried out is addition or subtraction.
1-bit comparator
2- bit comparator
Decoder
• Combinational circuit that has ‘n’ input lines
and maximum of 2^n output lines.
• One of the outputs will be active High based
on the combination of inputs present, when
the decoder is enabled.
• The outputs of the decoder are nothing but
the min terms of ‘n’ input variables lines,
when it is enabled
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2 to 4 Line Decoder
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2 to 4 Line Decoder
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2 to 4 Line Decoder
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3 to 8 decoder with active high outputs
Truth Table of 3:8 decoder
BCD to 7 Segment Display Decoder
A special decoder which can convert binary
coded decimals into another form which can be
easily displayed through a 7-segment display
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BCD to 7 Segment Display Decoder
45
BCD to 7 Segment Display Decoder
Two types
• Common Anode
• Common Cathode
46
BCD to 7 Segment Display Decoder
47
BCD to 7 Segment Display Decoder
48
BCD to 7 Segment Display Decoder
49
Encoders
• Combinational circuits that change the binary
information into N output lines
• The binary information is passed in the form of 2N
input lines.
• The output lines define the N-bit code for the binary
information.
50
4 to 2 Line Encoder
51
4 to 2 Line Encoder
A1 = Y1 + Y0
A0 = Y2 + Y0
Y0
Y1
Y2
52
8x3 Encoder
outputs
inputs
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
Multiplexers
• Multiplex means many into one.
• Multiplexer is a circuit with many inputs but only
one output.
• “MUX” is a combinational logic circuit designed
to switch one of several input lines through to a
single common output line by the application of
a control signal/select lines.
• The circuit has n input signals, m control signals
and 1 output signal.
Multiplexer Block diagram
8x1 mux using 4x1 mux and OR gate
8x1 mux using 4x1 mux and 2x1 mux
Multiplexer as fulladder
